The present invention relates generally to semiconductor devices and in particular to lateral bipolar transistors.
From early on it has been the goal of integrated-circuit development to integrate on a chip as many components as possible. Integration allows fabrication of smaller and faster systems that dissipate less power. While CMOS (complementary metal-oxide-semiconductor) technology, which has become predominant in the fabrication of integrated circuits, particularly digital circuits, allows high integration levels and low-cost fabrication, bipolar technology has re-gained intensive attention in recent time due to such advantages over CMOS devices as higher speed, higher current density, lower noise and higher cutoff frequency. One characteristic of bipolar devices that has been considered a drawback for a long time is the higher static power dissipation than in CMOS devices. However, this advantage of CMOS devices may disappear as their operating speed increases and the dynamic power dissipation of CMOS circuits becomes a significant factor.
Among bipolar transistors, vertical and lateral types can be distinguished. Vertical bipolar transistors can exhibit excellent performance; however, their fabrication requires a number of special processing steps, which makes their integration into a CMOS process a problem. Moreover, conventional vertical bipolar transistors are not very compact, thus limiting the achievable integration density. On the other hand, a lateral bipolar transistor, though typically considered as having lower performance than its vertical counterpart, is a transistor well-suited for integration into a CMOS process owing to many structural similarities between a lateral bipolar transistor and a MOSFET (metal-oxide-semiconductor field-effect transistor).
FIG. 1 depicts a conventional lateral bipolar transistor, such as known from, e.g., U.S. Pat. No. 5,567,631, which can be fabricated using a CMOS process. The transistor, designated 10, is fabricated in SOI (silicon-on-insulator) technology. In this technology, a thin single crystalline silicon layer resides on an insulating layer produced in a silicon substrate typically using a SIMOX (separation by implanted oxygen) process. The thin silicon layer serves as the active layer within which all circuit elements of an integrated circuit chip, such as transistors, diodes, capacitors, and resistors, are created. The presence of the insulator, which is usually a silicon dioxide, greatly reduces parasitic capacitances and allows easy separation and insulation of the circuit elements. In FIG. 1, reference numeral 12 designates the substrate, reference numeral 14 the insulating layer and reference numeral 16 the thin silicon-on-insulator layer.
Transistor 10 comprises spaced-apart emitter and collector regions 18, 20 as well as a base region 22 filling the space between emitter region 18 and collector region 20. Emitter region 18, base region 22 and collector region 20 are formed in lateral, juxtaposed arrangement in silicon layer 16. Emitter region 18 is a heavily doped region, whereas collector region 20 is composed of a lightly doped collector sub-region 20a and a heavily doped collector sub-region 20b. A polysilicon gate 24 overlays base region 22 and is insulated therefrom by an oxide layer 26. Gate 24 shields base region 22 during doping of silicon layer 16, thus defining the length of base region 22 as measured in a direction of distance between emitter region 18 and collector region 20. During operation of transistor 10, gate 24 has no function. Metal contacts 28, 30 for contacting emitter region 18 and collector region 20, respectively, are formed in contact holes 32 formed in a layer of silicon dioxide 34 deposited over transistor 10. Reference numeral 36 designates insulating spacers on the sidewalls of gate 24, and reference numeral 38 designates field oxide regions isolating transistor 10 from adjacent circuit structures.
As can be seen from FIG. 1, emitter region 18 and collector region 20 extend across the entire depth of silicon layer 16. This requires adoption of a side contact scheme for contacting base region 22. To this effect and as illustrated in FIG. 2, base region 22 extends beyond gate 24 in the width direction of transistor 10, thereby forming protruding end portions 40. A metal base contact 42 is formed on one of these end portions 40 of base region 22.
In bipolar transistors, the base resistance is one of the most important electrical parameters due to its critical impact on transistor performance. Achieving a low base resistance is a general goal underlying the work of transistor designers. Although the base contact 42 is close to the intrinsic part of base region 22 in the structure shown in FIGS. 1 and 2, the base resistance of transistor 10 is very high and increases with increasing device width. A large effective base width, however, is advantageous for achieving a high value of β, the common-emitter current gain expressed by β=IC/IB, where IC is the collector current and IB is the base current. Thus, the transistor design shown in FIGS. 1 and 2 imposes a tradeoff between the base resistance and the current gain β.
Other structures for lateral bipolar transistors in SOI have been proposed in order to reduce the base resistance. For example, reference is made to M. Chan et al.: “A High Performance Lateral Bipolar Transistor from a SOI CMOS Process”, Proc. 1995 IEEE Intern. SOI Conf., October 1995, pp. 90–91; and G. G. Shahidi et al.: “A Novel High-Performance Lateral Bipolar on SOI”, IEDM 1991, pp. 663–666. However, these structures are more complicated and introduce additional process complexity over the simple CMOS process.
It is therefore highly desirable to have a lateral bipolar transistor with improved base resistance, which easily integrates into a CMOS process.